MIRR Documentation Index

Canonical index for all project documentation. Updated each campaign.


Status Legend

StatusMeaning
ActiveCurrent, maintained documentation
FrozenHistorical, will not be updated
DeprecatedSuperseded by newer docs; kept for reference
StubPlaceholder awaiting content

Core Documentation

DocumentStatusDescription
RoadmapActiveProject phases, architecture, research foundation
TutorialActiveLearn MIRR from scratch
Type SystemActiveType checker reference (E601–E609)
Error CodesActiveError codes introduced per phase
Logic SimplificationActivePhase 3 simplifier architecture and rules
BenchmarksActiveCriterion benchmark tiers and usage
GlossaryActiveProject terminology and acronyms (~55 terms)
ContributingActiveCoding standards, campaign workflow, error allocation
FPGA Targets GuideActiveFPGA toolchain, synthesis, and target configuration
MAPE-K GuideActiveAutonomic feedback loop simulator and LTL monitoring
S-Expression GuideActiveHomoiconic S-expression IR, round-trip invariant

Architecture References

DocumentStatusDescription
R-SPU ISA v2 SpecificationActiveR-SPU instruction set architecture v2 specification
Migration GuideActiveBreaking changes per version
Phase 2 Temporal Guard CompilerFrozenOriginal Phase 2 design notes

Self-Hosting

DocumentStatusDescription
Self-Hosting MilestoneFrozenMIRR-in-MIRR progress tracker
Self-Hosting Core SpecFrozenCore language spec for self-hosting
Self-Hosting IR ContractFrozenIR contract for bootstrap pipeline

Legacy

DocumentStatusDescription
MIRR SpecDeprecatedPhase 1 minimal core only. See Tutorial and Type System.

Papers

DocumentStatusDescription
paper/dac2027-mirr.texFrozenDAC 2027 submission (tag: dac2027-submission)
paper/living-doc/ActiveLiving documentation (no page limit, updated every campaign)

Proposal Archive

All proposals live in proposals/ and follow the campaign workflow.

#CampaignDateStatus
001SEM-0012026-03-08Executed
002TYPE-0012026-03-08Executed
003TYPE-0022026-03-08Executed
004TYPE-0032026-03-08Executed
005TYPE-0042026-03-08Executed
006ROCQ-0012026-03-08Executed
007TYPE-005 + RSPU-0012026-03-08Executed
008DOC-0012026-03-08Executed
009SITE-0012026-03-09Executed
010SITE-0022026-03-09Executed
011SPAN-001 + LSP-0012026-03-09Executed
012ERR-001 + VSCODE-0012026-03-09Executed
013FPGA-0012026-03-09Executed
014FPGA-0022026-03-09Executed
015ERR-0022026-03-09Executed
016SAFE-0012026-03-09Executed
017DEBT-0012026-03-09Executed
018DEBT-0022026-03-09Executed
019DOC-0012026-03-09Executed
020DOC-0022026-03-09Executed
021SYNTH-0012026-03-09Executed
022PAPER-0012026-03-09Executed
023PHASE7-FOUNDATION2026-03-10Executed
024MEGA-1a2026-03-10Executed
025MEGA-1b2026-03-11Executed
026MEGA-22026-03-11Executed
027MEGA-32026-03-11Executed
028AUDIT-0012026-03-11Executed
029STD-0012026-03-12Executed
030LRA-0012026-03-11Executed
031LRA-0022026-03-11Executed
032STD-001-LRA2026-03-12Executed
033LRA-PHASE12026-03-12Executed
034LRA-PHASE22026-03-12Executed
035LRA-PHASE3-PHASE42026-03-12Executed

See Also

  • Home — Project landing page
  • Roadmap — Full project roadmap